top.map.summary

Analysis & Synthesis Status : Successful - Sun Mar 02 17:40:47 2008 Quartus II Version : 6.0 Build 202 06/20/2006 SP 1 SJ Full Version Revision Name : top Top-level Entity Name : top1 Family : Cyc

http://www.codebf.com/read/360581/10086735

top.cbx.xml

http://www.codebf.com/read/360581/10086775

top.cmp.kpt

http://www.codebf.com/read/360581/10086788

top.tan.rpt

Timing Analyzer report for top Sun Mar 02 17:40:58 2008 Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1.

http://www.codebf.com/read/360581/10086830

top.flow.rpt

Flow report for top Sun Mar 02 17:40:58 2008 Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Noti

http://www.codebf.com/read/360581/10086832

top.bld

Release 7.1.04i ngdbuild H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -intstyle ise -dd d:\test\icx229al/_ngo -nt timestamp -uc top.ucf -p xc3s400-pq208-4 t

http://www.codebf.com/read/359174/10162838

top.lfp

# begin LFP file D:\test\ICX229AL\top.lfp designfile top.ngd

http://www.codebf.com/read/359174/10162890

top.par_nlf

Release 7.1.04i - netgen H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: netgen -intstyle ise -s 4 -pcf top.pcf -sdf_anno true -w -ofmt verilog -sim top.ncd top_timesim

http://www.codebf.com/read/359174/10162940

top.cmd_log

sch2verilog -intstyle ise -family spartan3 -w top.sch top.vf xst -intstyle ise -ifn __projnav/top.xst -ofn top.syr sch2verilog -intstyle ise -family spartan3 -w top.sch top.vf xst -intstyle ise

http://www.codebf.com/read/359174/10163002

top.prj

verilog work "ICX229.v" verilog work "serial.v" verilog work "VSP2232.v" verilog work "clk4.v" verilog work "shuju.v" verilog work "top.vf"

http://www.codebf.com/read/359174/10163025