div-close.ftl

http://www.codebf.com/read/438920/1821351

div.ftl

http://www.codebf.com/read/438920/1821380

div-close.ftl

http://www.codebf.com/read/438920/1821396

div.ftl

http://www.codebf.com/read/438920/1821421

div-close.ftl

http://www.codebf.com/read/438920/1821436

div.pl

#!/usr/local/bin/perl # x86 assember sub bn_div_words { local($name)=@_; &function_begin($name,""); &mov("edx",&wparam(0)); # &mov("eax",&wparam(1)); # &mov("ebx",&wparam(2)); # &div("ebx");

http://www.codebf.com/read/433192/1885009

div.c

/* div.c - div file for stdlib */ /* Copyright 1992-2001 Wind River Systems, Inc. */ /* modification history -------------------- 01g,25sep01,gls fixed div_r to check for negative numerator (SPR #

http://www.codebf.com/read/432474/1892329

div.c

/* div.c - div file for stdlib */ /* Copyright 1992-2001 Wind River Systems, Inc. */ /* modification history -------------------- 01g,25sep01,gls fixed div_r to check for negative numerator (SPR #

http://www.codebf.com/read/431876/1902801

div.c

/* div.c - div file for stdlib */ /* Copyright 1992-2001 Wind River Systems, Inc. */ /* modification history -------------------- 01g,25sep01,gls fixed div_r to check for negative numerator (SPR #

http://www.codebf.com/read/428641/1957347

div.v

module div(clk,rst,clk_2,clk_4,clk_8); input clk,rst; output clk_2,clk_4,clk_8; reg [2:0]cnt8; wire clk_2,clk_4,clk_8; always @ (posedge clk or negedge rst) if (!rst) begin cnt8

http://www.codebf.com/read/427629/1969384