Timing Analyzer report for control
Sun Feb 25 04:50:01 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Noti
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
--
-- Definition of a dual port ROM for KCPSM2 or KCPSM3 program defined by control.psm
-- and assmbled using KCPSM2 or KCPSM3 assembler.
--
-- This file has been modified for use with the Designi
--
-- Definition of a dual port ROM for KCPSM2 or KCPSM3 program defined by control.psm
-- and assmbled using KCPSM2 or KCPSM3 assembler.
--
-- This file has been modified for use with the Designi
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
