verilog data packer verilog data packer verilog data packer

				The Data Packer stage concatenates variable length Huffman Codes and Categories and output them in fixed chunks. 
				
				The data packer module contains two Registers, Register A and B that hold data for output.  The length register contains length of valid data in Register A.  The End Pointer Register points to the end of valid data in Register B.  It is used to concatenate the data in Register A with the old data in Register B.  Initially as Register B is empty, it points to the end of Register B.  Later on as Register B gets filled with data, EndP value decreases accordingly.
				
				Lets see how it works.
				
				First the variable length Huffman Code and Category are concatenated in Register A.  The Length Register contains the length of data contained in Register A.  In the next Clock Cycle as new data arrives, this data is shifted into Register B.  The End pointer is updated to reflect where valid data ends.  It is referenced again in next clock cycle to concatenate new values with the old ones in Register B.  This is repeated again and again till 16 bit data is stored in Register B.  At this point, the control logic outputs these 16 bits of data with valid output pulse.  The remaining data is shifted to the end of Register B and EndP again updated.  This way data is packed and output.