`include "params.v"
/*-----------------------------------*/
// Module : CONTROL
// File : control.v
// Description : Description of Control Unit in Viterbi Decoder
// Simulator : Modelsim 4.6 / Windows 98
// Synthesizer : -
// Author : M Zalfany U (zalfany@opencores.org)
/*-----------------------------------*/
// Revision Number : 1
// Date of Change : 10th Jan 2000
// Modifier : Zalfany
// Description : Initial Design
/*-----------------------------------*/
module CONTROL (Reset, CLOCK, Clock1, Clock2, ACSPage, ACSSegment, Active,
CompareStart, Hold, Init, TB_EN);
input Reset, CLOCK, Active;
output [`WD_FSM-1:0] ACSSegment;
output [`WD_DEPTH-1:0] ACSPage;
output Clock1, Clock2;
output Hold, Init, CompareStart;
output TB_EN;
reg [`WD_FSM-1:0] ACSSegment;
reg [`WD_DEPTH-1:0] ACSPage;
reg Init,Hold;
wire EVENT_1,EVENT_0;
reg TB_EN;
reg CompareStart;
reg [3:0] CompareCount;
reg count,Clock1, Clock2;
// Clock1 and Clock2
always @(posedge CLOCK or negedge Reset)
if (~Reset) count
always @(posedge CLOCK or negedge Reset)
begin
if (~Reset)
begin
Clock1 Clock2 end
else
begin
if (count) Clock1 if (~count) Clock2 end
end
// ---
assign EVENT_1 = (ACSSegment == 6'h3E);
assign EVENT_0 = (ACSSegment == 6'h3F);
always @(posedge Clock1 or negedge Reset)
begin
if (~Reset)
begin
{ACSPage,ACSSegment} Init Hold TB_EN end
else if (Active)
begin
// Increase ACSSegment and Page
{ACSPage,ACSSegment}
// Init and Hold signal
if (EVENT_1) begin Init else if (EVENT_0) begin Init else begin {Init,Hold}
// enable TB after 63 sets of survivor created
if ((ACSSegment == 'h3F) && (ACSPage == 'h3E)) TB_EN end
end
// For the first K-1, no COMPARISON made. Survivor is coming from '0' branch.
always @(posedge Clock2 or negedge Reset)
begin
if (~Reset)
begin
CompareCount CompareStart end
else begin
if (~CompareStart && EVENT_1) CompareCount if (CompareCount == `CONSTRAINT-1 && EVENT_0) CompareStart end
end
endmodule
