用74181和74182设计的一个8位运算器 已通过仿真~~~~~~~~~~~~~~~~~~~~~

源代码在线查看: and-2.flow.rpt

软件大小: 198 K
上传用户: x395450030
关键词: 74181 74182 8位 运算器
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相关代码

				Flow report for and-2
				Tue Apr 07 20:02:52 2009
				Version 5.1 Build 176 10/26/2005 SJ Full Version
				
				
				---------------------
				; Table of Contents ;
				---------------------
				  1. Legal Notice
				  2. Flow Summary
				  3. Flow Settings
				  4. Flow Elapsed Time
				  5. Flow Log
				
				
				
				----------------
				; Legal Notice ;
				----------------
				Copyright (C) 1991-2005 Altera Corporation
				Your use of Altera Corporation's design tools, logic functions 
				and other software and tools, and its AMPP partner logic 
				functions, and any output files any of the foregoing 
				(including device programming or simulation files), and any 
				associated documentation or information are expressly subject 
				to the terms and conditions of the Altera Program License 
				Subscription Agreement, Altera MegaCore Function License 
				Agreement, or other applicable license agreement, including, 
				without limitation, that your use is for the sole purpose of 
				programming logic devices manufactured by Altera and sold by 
				Altera or its authorized distributors.  Please refer to the 
				applicable agreement for further details.
				
				
				
				+--------------------------------------------------------------------+
				; Flow Summary                                                       ;
				+-------------------------+------------------------------------------+
				; Flow Status             ; Successful - Tue Apr 07 20:02:52 2009    ;
				; Quartus II Version      ; 5.1 Build 176 10/26/2005 SJ Full Version ;
				; Revision Name           ; and-2                                    ;
				; Top-level Entity Name   ; and-2                                    ;
				; Family                  ; Cyclone                                  ;
				; Device                  ; EP1C6Q240C8                              ;
				; Timing Models           ; Final                                    ;
				; Met timing requirements ; Yes                                      ;
				; Total logic elements    ; 39 / 5,980 ( < 1 % )                     ;
				; Total pins              ; 34 / 185 ( 18 % )                        ;
				; Total virtual pins      ; 0                                        ;
				; Total memory bits       ; 0 / 92,160 ( 0 % )                       ;
				; Total PLLs              ; 0 / 2 ( 0 % )                            ;
				+-------------------------+------------------------------------------+
				
				
				+-----------------------------------------+
				; Flow Settings                           ;
				+-------------------+---------------------+
				; Option            ; Setting             ;
				+-------------------+---------------------+
				; Start date & time ; 04/07/2009 20:02:44 ;
				; Main task         ; Compilation         ;
				; Revision Name     ; and-2               ;
				+-------------------+---------------------+
				
				
				+-------------------------------------+
				; Flow Elapsed Time                   ;
				+----------------------+--------------+
				; Module Name          ; Elapsed Time ;
				+----------------------+--------------+
				; Analysis & Synthesis ; 00:00:01     ;
				; Fitter               ; 00:00:02     ;
				; Assembler            ; 00:00:01     ;
				; Timing Analyzer      ; 00:00:01     ;
				; Total                ; 00:00:05     ;
				+----------------------+--------------+
				
				
				------------
				; Flow Log ;
				------------
				quartus_map --read_settings_files=on --write_settings_files=off and-2 -c and-2
				quartus_fit --read_settings_files=off --write_settings_files=off and-2 -c and-2
				quartus_asm --read_settings_files=off --write_settings_files=off and-2 -c and-2
				quartus_tan --read_settings_files=off --write_settings_files=off and-2 -c and-2 --timing_analysis_only
				
				
				
							

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