一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog
源代码在线查看： top.v
module top(); // wires to connect top-level modules wire phi1; wire phi2; wire [1:0] command_s1; wire [4:0] address_s1; wire [22:0] data_s1; wire valid_s1; //////////////////////////////////////////////////////////////////////////////// // Module Instantiations //////////////////////////////////////////////////////////////////////////////// chip chip(phi1, phi2, command_s1, address_s1, data_s1, valid_s1); clkgen clkgen(phi1, phi2); test test(phi1, phi2, command_s1, address_s1, data_s1, valid_s1); // Magellan system tasks initial begin // Create a dump file for connectivity info after simulation $ssi_navdbase("nav.dbase", "top.v"); // Changes stored in a VCD file, an ASCII dump of sim results $dumpvars; end endmodule // top
