FPGA调试程序

				Fitter Status : Successful - Tue Nov 25 10:38:05 2008
				Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
				Revision Name : div
				Top-level Entity Name : div
				Family : ACEX1K
				Device : EP1K30QC208-3
				Timing Models : Final
				Total logic elements : 78 / 1,728 ( 5 % )
				Total pins : 7 / 147 ( 5 % )
				Total memory bits : 0 / 24,576 ( 0 % )
				Total PLLs : 0