学习Xilinx公司开发软件ISE的基础资料

				library LIB;
				use LIB.SYNOPSYS.all; 
				use LIB.AMD_PACK.all; 
				
				entity CONTROL is 
				  port(INSTRUCTION              : in INSTRUCTION_OPS; 
				       CONDITION_CODE           : in BIT; 
				       CONDITION_CODE_ENABLE    : in BIT; 
				       FORCE_LOAD               : in BIT; 
				       REGCNT_ZERO              : in BIT; 
				       UPC_CONTROL              : out UPC_OPS;
				       STACK_CONTROL            : out STACK_OPS; 
				       REGCNT_CONTROL           : out REGCNT_OPS; 
				       Y_CONTROL                : out Y_MUX_OPS; 
				       PIPELINE_ENABLE          : out BIT; 
				       MAPPING_ROM_ENABLE       : out BIT; 
				       INTERRUPT_VECTOR_ENABLE  : out BIT); 
				end CONTROL ; 
				
				architecture CONTROL_HDL of CONTROL is
				begin 
				
				  CONTROL_LOGIC: process (INSTRUCTION,CONDITION_CODE,CONDITION_CODE_ENABLE,
				                          FORCE_LOAD,REGCNT_ZERO)
				  begin 
				    PIPELINE_ENABLE 				    MAPPING_ROM_ENABLE 				    INTERRUPT_VECTOR_ENABLE 				    UPC_CONTROL 				    STACK_CONTROL 				    Y_CONTROL 				    if( FORCE_LOAD = '1') then 
				      REGCNT_CONTROL 				    else 
				      REGCNT_CONTROL 				    end if; 
				
				    case INSTRUCTION is 
				      -- Reset: clear stack and upc 
				      when JZ => 
				        UPC_CONTROL 				        STACK_CONTROL 				        Y_CONTROL 				        PIPELINE_ENABLE 				  
				      -- Cond jump sub: either jump via data input or just do next inst 
				      when CJS =>
				        PIPELINE_ENABLE 				        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
				          STACK_CONTROL 				          Y_CONTROL 				        end if; 
				  
				      -- Jump using map:
				      when JMAP =>
				        MAPPING_ROM_ENABLE 				        Y_CONTROL 				  
				      -- Cond jump: either jump or next inst
				      when CJP =>
				        PIPELINE_ENABLE 				        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
				          Y_CONTROL 					end if; 
				  
				      -- Push stack: stack gets next inst addr, usually as loop setup
				      when PUSH =>
				        STACK_CONTROL 				        PIPELINE_ENABLE 				        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
				  	  REGCNT_CONTROL 				        end if; 
				  
				      -- Push and cond jump sub (2-way) 
				      when JSRP =>
				        PIPELINE_ENABLE 				        STACK_CONTROL 				        if (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
				  	  Y_CONTROL 				        else 
				          Y_CONTROL 					end if; 
				  
				      -- Cond junk using vector interrupt
				      when CJV =>
				        INTERRUPT_VECTOR_ENABLE 				        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
				          Y_CONTROL 					end if; 
				        
				      -- Cond jump (2-way) 
				      when JRP =>
				        PIPELINE_ENABLE 				        if (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
				          Y_CONTROL 				        else
				          Y_CONTROL 					end if; 
				  
				      -- Repeat stack loop if cntr != '0'
				      when RFCT =>
				        PIPELINE_ENABLE 				        if( REGCNT_ZERO = '0') then 
				          Y_CONTROL 				  	  REGCNT_CONTROL 				        else 
				          STACK_CONTROL 				        end if; 
				  
				      -- Repeat D loop is cntr != 0 
				      when RPCT =>
				        PIPELINE_ENABLE 				        if( REGCNT_ZERO = '0') then 
				  	  Y_CONTROL 				  	  REGCNT_CONTROL 				        end if; 
				  
				      -- Conditional return 
				      when CRTN =>
				        PIPELINE_ENABLE 				        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
				  	  Y_CONTROL 				  	  STACK_CONTROL 				        end if; 
				  
				      -- Conditional jump and pop       
				      when CJPP =>
				        PIPELINE_ENABLE 				        if not (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
				  	  Y_CONTROL 				  	  STACK_CONTROL 				        end if; 
				        
				      -- Load counter/register
				      when LDCT =>
				        PIPELINE_ENABLE 				        REGCNT_CONTROL 				  
				      -- Test end of loop 
				      when LOP =>
				        PIPELINE_ENABLE 				        if (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
				  	  Y_CONTROL 				        else 
				  	  STACK_CONTROL 					end if; 
				        
				      -- Continue, no-op
				      when CONT =>
				        PIPELINE_ENABLE 				  
				      -- Three-way branch 
				      when TWB =>    
				        PIPELINE_ENABLE 				        if( REGCNT_ZERO = '0') then 
				          REGCNT_CONTROL 				  	  if (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
				  	    Y_CONTROL 				  	  else
				  	    STACK_CONTROL 				  	  end if; 
				        else
				  	  STACK_CONTROL 				  	  if (CONDITION_CODE_ENABLE = '0' and CONDITION_CODE = '1') then 
				  	    Y_CONTROL 				          end if; 
				  	end if; 
				
				    end case; 
				  end process CONTROL_LOGIC; 
				
				end CONTROL_HDL;