FPGA的串口通信程序

源代码在线查看: image.flow.rpt

软件大小: 1278 K
上传用户: maple_78
关键词: FPGA 串口通信 程序
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相关代码

				Flow report for image
				Mon Apr 21 09:41:48 2008
				Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
				
				
				---------------------
				; Table of Contents ;
				---------------------
				  1. Legal Notice
				  2. Flow Summary
				  3. Flow Settings
				  4. Flow Elapsed Time
				  5. Flow Log
				
				
				
				----------------
				; Legal Notice ;
				----------------
				Copyright (C) 1991-2005 Altera Corporation
				Your use of Altera Corporation's design tools, logic functions 
				and other software and tools, and its AMPP partner logic       
				functions, and any output files any of the foregoing           
				(including device programming or simulation files), and any    
				associated documentation or information are expressly subject  
				to the terms and conditions of the Altera Program License      
				Subscription Agreement, Altera MegaCore Function License       
				Agreement, or other applicable license agreement, including,   
				without limitation, that your use is for the sole purpose of   
				programming logic devices manufactured by Altera and sold by   
				Altera or its authorized distributors.  Please refer to the    
				applicable agreement for further details.
				
				
				
				+-------------------------------------------------------------------------+
				; Flow Summary                                                            ;
				+-------------------------+-----------------------------------------------+
				; Flow Status             ; Successful - Mon Apr 21 09:41:48 2008         ;
				; Quartus II Version      ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
				; Revision Name           ; image                                         ;
				; Top-level Entity Name   ; image                                         ;
				; Family                  ; Cyclone                                       ;
				; Device                  ; EP1C6T144C8                                   ;
				; Timing Models           ; Final                                         ;
				; Met timing requirements ; No                                            ;
				; Total logic elements    ; 991 / 5,980 ( 16 % )                          ;
				; Total pins              ; 60 / 98 ( 61 % )                              ;
				; Total virtual pins      ; 0                                             ;
				; Total memory bits       ; 0 / 92,160 ( 0 % )                            ;
				; Total PLLs              ; 1 / 2 ( 50 % )                                ;
				+-------------------------+-----------------------------------------------+
				
				
				+-----------------------------------------+
				; Flow Settings                           ;
				+-------------------+---------------------+
				; Option            ; Setting             ;
				+-------------------+---------------------+
				; Start date & time ; 04/21/2008 09:40:58 ;
				; Main task         ; Compilation         ;
				; Revision Name     ; image               ;
				+-------------------+---------------------+
				
				
				+-------------------------------------+
				; Flow Elapsed Time                   ;
				+----------------------+--------------+
				; Module Name          ; Elapsed Time ;
				+----------------------+--------------+
				; Analysis & Synthesis ; 00:00:18     ;
				; Fitter               ; 00:00:23     ;
				; Assembler            ; 00:00:02     ;
				; Timing Analyzer      ; 00:00:02     ;
				; Total                ; 00:00:45     ;
				+----------------------+--------------+
				
				
				------------
				; Flow Log ;
				------------
				quartus_map --read_settings_files=on --write_settings_files=off image -c image
				quartus_fit --read_settings_files=off --write_settings_files=off image -c image
				quartus_asm --read_settings_files=off --write_settings_files=off image -c image
				quartus_tan --read_settings_files=off --write_settings_files=off image -c image --timing_analysis_only
				
				
				
							

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