fpga功能实现有限字长响应FIR 用verilog编写

				module control(clk1,clk2,i,OE,reset);				parameter state_reset=9;				parameter state_spare=8;				input clk1,clk2;				output[2:0] i;				output OE;				output reset;				reg reset;				reg OE;				reg[2:0] i;				reg[3:0] state,next_state;				always @(posedge clk1)				    state				always @(posedge clk2)				   state								always @(state)				begin				    case(state)				        state_reset:begin next_state=0;reset=0;OE=0;i=7;end				        0:begin next_state=1;reset=1;OE=0;i=0;end				        1:begin next_state=2;reset=1;OE=0;i=1;end				        2:begin next_state=3;reset=1;OE=0;i=2;end				        3:begin next_state=4;reset=1;OE=0;i=3;end				        4:begin next_state=5;reset=1;OE=0;i=4;end				        5:begin next_state=6;reset=1;OE=0;i=5;end				        6:begin next_state=7;reset=1;OE=0;i=6;end				        7:begin next_state=state_spare;OE=0;i=7;end				        state_spare:begin next_state=state_spare;reset=1;OE=1;i=7;end				        				        default begin next_state=ok;reset=1;OE=0;i=7;end				    endcase				end				    				endmodule