一个verilog实现的crc校验

源代码在线查看: readme

软件大小: 1407 K
上传用户: wyly
关键词: verilog crc
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								WHAT's WHERE?:								- Directories and files:					README: This file					script, stop: bash scripts to avoid having to type too much.					/data: input data used to verify the different blocks of the CRC Generator.					/vhdl: All the VHDL files (note: the path of the data files in the testbench files should be edited)					/syn, WORK: directories used by the Synthesis software.					/DOCS: The documentation files.						CRC_report.ps/.pdf  : The documentation plus the license and a verbatim copy of the file.						crc-generator.html  : Short description of the project (as in opencores.org)						CRC_ie3_contest.pdf : The paper presented at the IEEE Student Paper Contest in Cairo, Egypt.								      It shows the main highlights of the design and the algorithm.								      							

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