用VHDL语言编写的DDS正弦函数发生器

				-- megafunction wizard: %LPM_ADD_SUB%
				-- GENERATION: STANDARD
				-- VERSION: WM1.0
				-- MODULE: lpm_add_sub 
				
				-- ============================================================
				-- File Name: ADD.vhd
				-- Megafunction Name(s):
				-- 			lpm_add_sub
				-- ============================================================
				-- ************************************************************
				-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
				--
				-- 6.0 Build 178 04/27/2006 SJ Full Version
				-- ************************************************************
				
				
				--Copyright (C) 1991-2006 Altera Corporation
				--Your use of Altera Corporation's design tools, logic functions 
				--and other software and tools, and its AMPP partner logic 
				--functions, and any output files any of the foregoing 
				--(including device programming or simulation files), and any 
				--associated documentation or information are expressly subject 
				--to the terms and conditions of the Altera Program License 
				--Subscription Agreement, Altera MegaCore Function License 
				--Agreement, or other applicable license agreement, including, 
				--without limitation, that your use is for the sole purpose of 
				--programming logic devices manufactured by Altera and sold by 
				--Altera or its authorized distributors.  Please refer to the 
				--applicable agreement for further details.
				
				
				LIBRARY ieee;
				USE ieee.std_logic_1164.all;
				
				LIBRARY lpm;
				USE lpm.all;
				
				ENTITY ADD IS
					PORT
					(
						clock		: IN STD_LOGIC ;
						dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
						result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
					);
				END ADD;
				
				
				ARCHITECTURE SYN OF add IS
				
					SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
					SIGNAL sub_wire1_bv	: BIT_VECTOR (31 DOWNTO 0);
					SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
				
				
				
					COMPONENT lpm_add_sub
					GENERIC (
						lpm_direction		: STRING;
						lpm_hint		: STRING;
						lpm_pipeline		: NATURAL;
						lpm_type		: STRING;
						lpm_width		: NATURAL
					);
					PORT (
							dataa	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
							datab	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
							clock	: IN STD_LOGIC ;
							result	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
					);
					END COMPONENT;
				
				BEGIN
					sub_wire1_bv(31 DOWNTO 0) 					sub_wire1    					result    				
					lpm_add_sub_component : lpm_add_sub
					GENERIC MAP (
						lpm_direction => "ADD",
						lpm_hint => "ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO",
						lpm_pipeline => 1,
						lpm_type => "LPM_ADD_SUB",
						lpm_width => 32
					)
					PORT MAP (
						dataa => dataa,
						datab => sub_wire1,
						clock => clock,
						result => sub_wire0
					);
				
				
				
				END SYN;
				
				-- ============================================================
				-- CNX file retrieval info
				-- ============================================================
				-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
				-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
				-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
				-- Retrieval info: PRIVATE: ConstantB NUMERIC "995000"
				-- Retrieval info: PRIVATE: Function NUMERIC "0"
				-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
				-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
				-- Retrieval info: PRIVATE: Latency NUMERIC "1"
				-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
				-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
				-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
				-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
				-- Retrieval info: PRIVATE: ValidCtB NUMERIC "1"
				-- Retrieval info: PRIVATE: WhichConstant NUMERIC "2"
				-- Retrieval info: PRIVATE: aclr NUMERIC "0"
				-- Retrieval info: PRIVATE: clken NUMERIC "0"
				-- Retrieval info: PRIVATE: nBit NUMERIC "32"
				-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
				-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO"
				-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
				-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
				-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
				-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
				-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
				-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
				-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
				-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
				-- Retrieval info: CONNECT: @datab 0 0 32 0 995000 0 0 0 0
				-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
				-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
				-- Retrieval info: GEN_FILE: TYPE_NORMAL ADD.vhd TRUE
				-- Retrieval info: GEN_FILE: TYPE_NORMAL ADD.inc FALSE
				-- Retrieval info: GEN_FILE: TYPE_NORMAL ADD.cmp FALSE
				-- Retrieval info: GEN_FILE: TYPE_NORMAL ADD.bsf TRUE
				-- Retrieval info: GEN_FILE: TYPE_NORMAL ADD_inst.vhd TRUE