本代码介绍了使用VHDL开发FPGA的一般流程

				Release 6.2i - ngdbuild G.28				Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.								Command Line: ngdbuild -intstyle ise -dd e:\lvbin\freq_counter/_ngo -uc top.ucf
				-p xc2s100-pq208-6 top.ngc top.ngd 								Reading NGO file "E:/lvbin/Freq_counter/top.ngc" ...				Reading component libraries for design expansion...								Annotating constraints to design from file "top.ucf" ...								Checking timing specifications ...				Checking expanded design ...				WARNING:NgdBuild:477 - clock net 'CLK_BUFGP' has non-clock connections. These
				   problematic connections include:				     pin I0 on block U2_CP1 with type LUT2				WARNING:NgdBuild:478 - clock net 'CLK_BUFGP' drives no clock pins								NGDBUILD Design Results Summary:				  Number of errors:     0				  Number of warnings:   2								Total memory usage is 41184 kilobytes								Writing NGD file "top.ngd" ...								Writing NGDBUILD log file "top.bld"...