FPGA-CPLD_DesignTool(8-9-10)源代码

				 
				-w
				-g DebugBitstream:No
				-g Binary:no
				-g CRC:Enable
				-g ConfigRate:4
				-g CclkPin:PullUp
				-g M0Pin:PullUp
				-g M1Pin:PullUp
				-g M2Pin:PullUp
				-g ProgPin:PullUp
				-g DonePin:PullUp
				-g PowerdownPin:PullUp
				-g TckPin:PullUp
				-g TdiPin:PullUp
				-g TdoPin:PullUp
				-g TmsPin:PullUp
				-g UnusedPin:PullDown
				-g UserID:0xFFFFFFFF
				-g DCMShutDown:Disable
				-g DisableBandgap:No
				-g FreezeDCI:Yes
				-g StartUpClk:CClk
				-g DONE_cycle:4
				-g GTS_cycle:5
				-g GWE_cycle:6
				-g LCK_cycle:NoWait
				-g Match_cycle:Auto
				-g Security:None
				-g DonePipe:No
				-g DriveDone:No
				-g Encrypt:No