FPGA-CPLD_DesignTool,事例程序1-2

				 
				-w
				-g DebugBitstream:No
				-g Binary:no
				-g Gclkdel0:11111
				-g Gclkdel1:11111
				-g Gclkdel2:11111
				-g Gclkdel3:11111
				-g ConfigRate:4
				-g CclkPin:PullUp
				-g M0Pin:PullUp
				-g M1Pin:PullUp
				-g M2Pin:PullUp
				-g ProgPin:PullUp
				-g DonePin:PullUp
				-g TckPin:PullUp
				-g TdiPin:PullUp
				-g TdoPin:PullUp
				-g TmsPin:PullUp
				-g UnusedPin:PullDown
				-g UserID:0xFFFFFFFF
				-g StartUpClk:CClk
				-g DONE_cycle:4
				-g GTS_cycle:5
				-g GSR_cycle:6
				-g GWE_cycle:6
				-g LCK_cycle:NoWait
				-g Security:None
				-g DonePipe:No
				-g DriveDone:No