--
-- 两个三位二进制数的加法，结果由数码管显示
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY add IS
PORT (
a : IN std_logic_vector(2 DOWNTO 0);
b : IN std_logic_vector(2 DOWNTO 0);
c : OUT std_logic_vector(7 DOWNTO 0);
en : OUT std_logic_vector(7 DOWNTO 0));
END add;
ARCHITECTURE arch OF add IS
SIGNAL c_tmp : std_logic_vector(3 DOWNTO 0);
BEGIN
en c_tmp
PROCESS(c_tmp)
BEGIN
CASE c_tmp IS
WHEN "0000" =>
c WHEN "0001" =>
c WHEN "0010" =>
c WHEN "0011" =>
c WHEN "0100" =>
c WHEN "0101" =>
c WHEN "0110" =>
c WHEN "0111" =>
c WHEN "1000" =>
c WHEN "1001" =>
c WHEN "1010" =>
c WHEN "1011" =>
c WHEN "1100" =>
c WHEN "1101" =>
c WHEN "1110" =>
c WHEN "1111" =>
c WHEN OTHERS =>
NULL;
END CASE;
END PROCESS;
END arch;
