在quartus开发环境下

				library ieee;
				use ieee.std_logic_1164.all;
				use ieee.std_logic_unsigned.all;
				entity add is
				port(a,b,ci:in std_logic;
				     s,co:out std_logic);
				end;
				architecture one of add is
				signal temp:std_logic_vector(1 downto 0);
				begin
				temp				s				co				end;