Xilinx的modelsim 仿真库！里面有许多库函数
源代码在线查看： _primary.vhd
library verilog; use verilog.vl_types.all; entity gt is generic( align_comma_msb : string := "FALSE"; chan_bond_limit : integer := 16; chan_bond_mode : string := "OFF"; chan_bond_offset: integer := 8; chan_bond_one_shot: string := "FALSE"; chan_bond_seq_1_1: integer := 0; chan_bond_seq_1_2: integer := 0; chan_bond_seq_1_3: integer := 0; chan_bond_seq_1_4: integer := 0; chan_bond_seq_2_1: integer := 0; chan_bond_seq_2_2: integer := 0; chan_bond_seq_2_3: integer := 0; chan_bond_seq_2_4: integer := 0; chan_bond_seq_2_use: string := "FALSE"; chan_bond_seq_len: integer := 1; chan_bond_wait : integer := 8; clk_correct_use : string := "TRUE"; clk_cor_insert_idle_flag: string := "FALSE"; clk_cor_keep_idle: string := "FALSE"; clk_cor_repeat_wait: integer := 1; clk_cor_seq_1_1 : integer := 0; clk_cor_seq_1_2 : integer := 0; clk_cor_seq_1_3 : integer := 0; clk_cor_seq_1_4 : integer := 0; clk_cor_seq_2_1 : integer := 0; clk_cor_seq_2_2 : integer := 0; clk_cor_seq_2_3 : integer := 0; clk_cor_seq_2_4 : integer := 0; clk_cor_seq_2_use: string := "FALSE"; clk_cor_seq_len : integer := 1; comma_10b_mask : integer := 1016; crc_end_of_pkt : string := "K29_7"; crc_format : string := "USER_MODE"; crc_start_of_pkt: string := "K27_7"; dec_mcomma_detect: string := "TRUE"; dec_pcomma_detect: string := "TRUE"; dec_valid_comma_only: string := "TRUE"; mcomma_10b_value: integer := 768; mcomma_detect : string := "TRUE"; pcomma_10b_value: integer := 248; pcomma_detect : string := "TRUE"; rx_buffer_use : string := "TRUE"; rx_crc_use : string := "FALSE"; rx_data_width : integer := 2; rx_decode_use : string := "TRUE"; rx_loss_of_sync_fsm: string := "TRUE"; rx_los_invalid_incr: integer := 1; rx_los_threshold: integer := 4; serdes_10b : string := "FALSE"; termination_imp : integer := 50; tx_buffer_use : string := "TRUE"; tx_crc_force_value: integer := 214; tx_crc_use : string := "FALSE"; tx_data_width : integer := 2; tx_diff_ctrl : integer := 500; tx_preemphasis : integer := 0 ); port( chbonddone : out vl_logic; chbondo : out vl_logic_vector(3 downto 0); configout : out vl_logic; rxbufstatus : out vl_logic_vector(1 downto 0); rxchariscomma : out vl_logic_vector(3 downto 0); rxcharisk : out vl_logic_vector(3 downto 0); rxcheckingcrc : out vl_logic; rxclkcorcnt : out vl_logic_vector(2 downto 0); rxcommadet : out vl_logic; rxcrcerr : out vl_logic; rxdata : out vl_logic_vector(31 downto 0); rxdisperr : out vl_logic_vector(3 downto 0); rxlossofsync : out vl_logic_vector(1 downto 0); rxnotintable : out vl_logic_vector(3 downto 0); rxrealign : out vl_logic; rxrecclk : out vl_logic; rxrundisp : out vl_logic_vector(3 downto 0); txbuferr : out vl_logic; txkerr : out vl_logic_vector(3 downto 0); txn : out vl_logic; txp : out vl_logic; txrundisp : out vl_logic_vector(3 downto 0); chbondi : in vl_logic_vector(3 downto 0); configenable : in vl_logic; configin : in vl_logic; enchansync : in vl_logic; enmcommaalign : in vl_logic; enpcommaalign : in vl_logic; loopback : in vl_logic_vector(1 downto 0); powerdown : in vl_logic; refclk : in vl_logic; refclk2 : in vl_logic; refclksel : in vl_logic; rxn : in vl_logic; rxp : in vl_logic; rxpolarity : in vl_logic; rxreset : in vl_logic; rxusrclk : in vl_logic; rxusrclk2 : in vl_logic; txbypass8b10b : in vl_logic_vector(3 downto 0); txchardispmode : in vl_logic_vector(3 downto 0); txchardispval : in vl_logic_vector(3 downto 0); txcharisk : in vl_logic_vector(3 downto 0); txdata : in vl_logic_vector(31 downto 0); txforcecrcerr : in vl_logic; txinhibit : in vl_logic; txpolarity : in vl_logic; txreset : in vl_logic; txusrclk : in vl_logic; txusrclk2 : in vl_logic ); end gt;
