Xilinx Ise 官方源代码盘 第四章

				@P:  Worst Slack : 2.464
				@P:  hdl_demo|clk - Estimated Frequency : 237.9 MHz
				@P:  hdl_demo|clk - Requested Frequency : 150.0 MHz
				@P:  hdl_demo|clk - Estimated Period : 4.203
				@P:  hdl_demo|clk - Requested Period : 6.667
				@P:  hdl_demo|clk - Slack : 2.464
				@P: hdl_demo Part : xc2vp2fg256-7
				@P: hdl_demo I/O primitives : 60
				@P: hdl_demo I/O Register bits : 0
				@P: hdl_demo Register bits (Non I/O) : 22 (0%)
				@P: hdl_demo Total Luts : 60 (2%)