设计与验证verilog hdl

源代码在线查看: generic.srd

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关键词: verilog hdl
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相关代码

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				f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 1
				f "c:\prj\example-4-10\decode\if_single\if_single_decode.v"; #file 2
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