设计与验证verilog hdl

				f "noname"; #file 0
				f "noname"; #file 1
				f "c:\eda\synplicity\fpga_81\lib\lucent\xp.v"; #file 2
				f "c:\prj\chapter5\example-5-7\source\mod_copy2.v"; #file 3
				VNAME 'LUCENT.VLO.PRIM'; # view id 0
				VNAME 'LUCENT.OB.PRIM'; # view id 1
				VNAME 'LUCENT.IB.PRIM'; # view id 2
				VNAME 'work.mod_copy1.verilog'; # view id 3
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