该工程文件实现ARM系统中CPLD的逻辑工作
源代码在线查看： vz_ver4.data
MODELDATA
MODELDATA_VERSION "v1998.8"
DESIGN "vz_ver4";
/* port drive, load, max capacitance and max transition in data file */
PORTDATA
CLK: MAXTRANS(0.0);
CLK_RST: MAXTRANS(0.0);
A22: MAXTRANS(0.0);
A21: MAXTRANS(0.0);
A20: MAXTRANS(0.0);
EXTCE: MAXTRANS(0.0);
DISPLAY: MAXTRANS(0.0);
RSTIN: MAXTRANS(0.0);
HPICE: MAXTRANS(0.0);
NICCE: MAXTRANS(0.0);
DON: MAXTRANS(0.0);
RST_VZ: MAXTRANS(0.0);
SYNC: MAXTRANS(0.0);
ENDPORTDATA
/* timing arc data */
TIMINGDATA
ARCDATA
DISPLAY_DON_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A21_HPICE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A22_HPICE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
EXTCE_HPICE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A20_HPICE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A22_NICCE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A20_NICCE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
EXTCE_NICCE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
A21_NICCE_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
RSTIN_RST_VZ_delay:
CELL_RISE(scalar) {
VALUES("10");
}
CELL_FALL(scalar) {
VALUES("10");
}
ENDARCDATA
ARCDATA
CLK_SYNC_delay:
CELL_RISE(scalar) {
VALUES("10.2");
}
CELL_FALL(scalar) {
VALUES("10.2");
}
ENDARCDATA
ENDTIMINGDATA
ENDMODELDATA
