51的VERILOG代码！适用于Xilinx的FPGA
源代码在线查看： entries
/cast.out/1.3/Mon Sep 30 15:24:12 2002// /counter_test.out/1.3/Mon Sep 30 15:24:12 2002// /div16u.out/1.3/Mon Sep 30 15:24:12 2002// /divmul.out/1.3/Mon Sep 30 15:24:12 2002// /fib.out/1.3/Mon Sep 30 15:24:12 2002// /gcd.out/1.3/Mon Sep 30 15:24:12 2002// /int2bin.out/1.3/Mon Sep 30 15:24:12 2002// /interrupt_test.out/1.3/Mon Sep 30 15:24:12 2002// /lcall.out/1.3/Mon Sep 30 15:24:12 2002// /ncelab.out/1.3/Mon Sep 30 15:24:12 2002// /ncprep.out/1.1.1.1/Mon Jul 29 13:33:16 2002// /ncvlog.out/1.1.1.1/Mon Jul 29 13:33:16 2002// /negcnt.out/1.3/Mon Sep 30 15:24:12 2002// /r_bank.out/1.3/Mon Sep 30 15:24:12 2002// /serial_test.out/1.3/Mon Sep 30 15:24:12 2002// /sort.out/1.3/Mon Sep 30 15:24:12 2002// /sqroot.out/1.3/Mon Sep 30 15:24:12 2002// /testall.out/1.3/Mon Sep 30 15:24:12 2002// /timer.out/1.1.1.1/Mon Jul 29 13:33:17 2002// /timer_test.out/1.3/Mon Sep 30 15:24:12 2002// /xram_m.out/1.3/Mon Sep 30 15:24:12 2002// /xrom_m.out/1.1.1.1/Mon Jul 29 13:33:17 2002// D/waves.shm////
