VCS-verilog compiled simulator

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• VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式.该文档是一个不错的使用指南.免费下载

  资源简介：VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式.该文档是一个不错的使用指南.

  标签： VCS-verilog simulator compiled synopsys

  上传时间： 2014-11-17

  上传用户：lili123

• crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC de免费下载

  资源简介：crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.

  标签： Verilog VHDL and for

  上传时间： 2015-07-10

  上传用户：15736969615

• it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x免费下载

  资源简介：it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.

  标签： synthesize simulator modelsim interin

  上传时间： 2017-03-22

  上传用户：洛木卓

• it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xin免费下载

  资源简介：it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]

  标签： synthesize simulator modelsim digital

  上传时间： 2014-01-10

  上传用户：kernaling

• it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8免费下载

  资源简介：it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is requir...

  标签： synthesize simulator modelsim verilog

  上传时间： 2014-06-26

  上传用户：zhuyibin

• 这个手册将向你介绍使用NC-Verilog simulator和SimVision。免费下载

  资源简介：这个手册将向你介绍使用NC-Verilog simulator和SimVision。

  标签： NC-Verilog simulator SimVision

  上传时间： 2017-07-22

  上传用户：daoxiang126

• Verilog编码中的非阻塞性赋值免费下载

  资源简介：  One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simula...

  标签： Verilog 编码 非阻塞性赋值

  上传时间： 2013-10-17

  上传用户：tb_6877751

• Verilog编码中的非阻塞性赋值免费下载

  资源简介：  One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simula...

  标签： Verilog 编码 非阻塞性赋值

  上传时间： 2013-11-01

  上传用户：xzt

• What is Verilog? &#10149 Verilog HDL is a Hardware Description Language (HDL) &#10149 Verilog HDL免费下载

  资源简介：What is Verilog? &#10149 Verilog HDL is a Hardware Description Language (HDL) &#10149 Verilog HDL allows describe designs at a high level of abstraction as well as the lower implementation levels &#10149 Primary use of HDLs is the simul...

  标签： Verilog HDL 10149 Description

  上传时间： 2017-02-18

  上传用户：kjl

• VCS简明使用教程免费下载

  资源简介：仿真的过程编译Compile VCS对源文件进行编译，生成中间文件和可执行文件仿真Simulate运行可执行文件，对设计进行仿真调试通过观察波形、设置断点、追踪信号、查看schematic等来发现错误，并进行纠正覆盖率测试通过在编译时，加入覆盖率测试的选项、仿真后，生...

  标签： vcs

  上传时间： 2022-07-01

  上传用户：tigerwxf1