state strech routing protocl

相 关 资 源

• state strech routing protocl免费下载

  资源简介：state strech routing protocl

  标签： routing protocl strech state

  上传时间： 2017-03-15

  上传用户：bibirnovis

• Optimized Link State Routing是IETF正在研究的、用于移动式无线行动网络（这里免费下载

  资源简介：Optimized Link State Routing是IETF正在研究的、用于移动式无线行动网络（这里，不仅终端用户可移动，路由器和服务器等也可以）的几个协议之一。该项目的实施弥补了Hipercom项目的一个内容。

  标签： Optimized Routing State Link

  上传时间： 2015-04-27

  上传用户：851197153

• UM-OLSR is an OLSR (Optimized Link State Routing protocol) implementation for the ns2 network simula免费下载

  资源简介：UM-OLSR is an OLSR (Optimized Link State Routing protocol) implementation for the ns2 network simulator.

  标签： implementation Optimized protocol UM-OLSR

  上传时间： 2016-11-06

  上传用户：zaizaibang

• State Machine Coding Styles for Synthesis免费下载

  资源简介：  本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's ...

  标签： Synthesis Machine Coding Styles

  上传时间： 2013-10-15

  上传用户：dancnc

• Design Safe Verilog State Machine（Synplicity）免费下载

  资源简介：  One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, o...

  标签： Synplicity Machine Verilog Design

  上传时间： 2013-10-23

  上传用户：司令部正军级

• Creating Safe State Machines(Mentor)免费下载

  资源简介：  Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit....

  标签： Creating Machines Mentor State

  上传时间： 2013-10-08

  上传用户：wangzhen1990

• State Machine Coding Styles for Synthesis免费下载

  资源简介：  本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's ...

  标签： Synthesis Machine Coding Styles

  上传时间： 2013-10-12

  上传用户：sardinescn

• Design Safe Verilog State Machine（Synplicity）免费下载

  资源简介：  One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, o...

  标签： Synplicity Machine Verilog Design

  上传时间： 2013-10-20

  上传用户：苍山观海

• Creating Safe State Machines(Mentor)免费下载

  资源简介：  Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit....

  标签： Creating Machines Mentor State

  上传时间： 2013-11-02

  上传用户：xauthu

• Unique net-enabled GUI system based state of the art coding solutions with strong XML support.免费下载

  资源简介：Unique net-enabled GUI system based state of the art coding solutions with strong XML support.

  标签： net-enabled solutions support Unique

  上传时间： 2013-12-24

  上传用户：1101055045